This invention is in the field of integrated circuits, and is more specifically directed to such circuits for generating periodic signals of selected frequency and phase characteristics.
As is fundamental in the art, many modem electronic systems now include numerous integrated circuits that operate in conjunction with one another. In complex high performance systems such as modem personal computers and workstations, these integrated circuits typically operate in a synchronous manner relative to a system clock. In consumer-oriented systems such as televisions and home theaters, operation is synchronized with respect to a synchronization pulse that is included within the display signal itself. In these and other electronic systems, the generation of periodic signals for clocking the operation of circuit functions, with such generated signals based upon the system clock or synchronization pulse, is a common and somewhat critical function.
A conventional approach for generating periodic signals based upon a reference clock utilizes the well-known phase-locked loop, or PLL. In general, PLL circuits operate by comparing the time at which an edge of the reference clock is received relative to a corresponding edge of an internally generated clock. If a significant delay between these two edges is detected, the generation of the internal clock is adjusted to more closely match the received reference clock. In conventional analog PLLs, the frequency of a periodic signal produced by a voltage controlled oscillator is adjusted in response to a filtered signal from a phase detector, such that the instantaneous frequency of the internal chip clock is advanced or retarded depending upon whether the chip clock lags or leads the system clock. Analog PLLs therefore adjust the phase of the chip clock in a substantially continuous manner in response to a phase difference between the internal chip clock and the system clock; this smooth operation generally depends upon the filtering of the output of the phase detector circuit, but can be made quite wellbehaved in most implementations. Additionally, with the use of frequency dividers in the forward and feedback loops, analog PLLs can be used to generate periodic signals of a selectable frequency multiple of the input reference clock.
Modern digital integrated circuits generally use digital circuitry to generate multiple internal chip clocks that are based upon the output of a PLL. The digitally-generated clock signals can only be adjusted to a discrete accuracy that corresponds to the minimum step size of the digital clock generation circuitry. This incremental change in phase is often noticeable, particularly at high frequencies. The resulting "phase jitter" is now a commonly specified parameter for digital clock circuitry, as this effect is often a limiting factor in the accuracy and performance of the circuit.
In addition to phase jitter, the performance of PLL-based clock circuits in response to phase drift is another important parameter. Phase drift, which refers to the variation in the phase of a generated clock relative to the reference clock over time, can be caused by the accumulation of error over a number of clock cycles. Additionally, phase drift can also be caused by temperature and power supply voltage variations, and system noise.
Certain applications of clock generation circuitry are more sensitive to one of these parameters than to the other. A particularly difficult circuit application of clock generation circuitry is video decoding to convert television signals (transmitted or recorded) into digital data for computer display or digital video processing. As is well known in the art, conventional television signals included a synchronization pulse at the beginning of each scan line; in the case of a broadcast signal, this synchronization pulse is transmitted, while in the case of a video tape, the synchronization pulse is part of the recorded information. Color information is communicated within each scan line by way of the phase relationship of the color burst signal for each horizontal display location to the synchronization pulse. In order to achieve the desired accuracy in the displayed image, a video decoder system must be able to resolve relatively small phase variations (e.g., on the order of 10.degree.) in the color burst signal which occur at relatively long times (e.g., as long as 60 .mu.sec after a 6 MHz synchronization pulse). In order to carry out the desired video decoding of such a signal, the video decoder must be capable of generating a clock signal that has very little drift over time, for example with as little as 1 nsec drift over 60 .mu.sec.
The concept of using multiple phases of a PLL-generated clock signal to synthesize frequency is known in the art, as will now be described with reference to FIG. 1. FIG. 1 illustrates an exemplary PLL-based clock circuit 2 utilizing this known concept. Clock circuit 2 includes a phase-locked loop (PLL) that includes phase-frequency detector (PFD) 4 for comparing the relative phases of a reference clock on line CREF and a feedback clock on line CFB; the output of PFD 4 is applied to charge pump 6, in the conventional manner, which generates a voltage level corresponding to the phase difference between the reference and feedback clocks CREF, CFB, respectively. This voltage level, after filtering by low pass filter 8, is applied to a control input of voltage controlled oscillator (VCO) 10. VCO 10, in the conventional manner, generates a periodic waveform at a frequency controlled by this voltage at its control input, from charge pump 6. Accordingly, the frequency of the clock signal or signals generated by VCO 10 is controlled according to the phase relationship of the reference and feedback clocks CREF, CFB, applied to PFD 4, as will become apparent from the following description.
In this clock circuit 2, VCO 10 provides multiple phases (numbering n in this example) of the periodic clock signal. As shown in FIG. 1, these multiple phases are evenly spaced relative to one another over a period of the output signal. For example, considering output clock signal C.sub.0 as a baseline, VCO 10 in this example also generates a clock signal C.sub.1 that lags clock signal C.sub.0 by phase lag .DELTA..sub.1 ; additional clock signals C.sub.i are produced which lag clock signal C.sub.0 by a phase lag corresponding to index i times the phase lag .DELTA..sub.1. The nth clock signal C.sub.n lags clock signal C.sub.0 by a phase lag .DELTA..sub.n, which equals n.DELTA..sub.1, in this example. One of these clock signals is used as feedback clock CFB, after division by frequency divider 12. The provision of frequency divider 12 permits the base frequency of VCO 10 to differ from that of the reference clock CREF.
In operation, of course, the PLL portion of clock circuit 2 generates a periodic signal from VCO 10 that has its frequency adjusted so that the feedback clock on line CFB becomes phase-synchronous with the reference clock CREF. For example, if reference clock CREF leads feedback clock CFB, as detected by PFD 4, charge pump 6 adjusts the voltage at its output to control VCO 10 to increase the frequency of its output clock signals C; conversely, if reference dock CREF lags feedback clock CFB, charge pump 6 adjusts the voltage at its output in the other direction, to control VCO 10 to reduce the frequency of its output clocks. After a sufficient number of cycles, and assuming a relatively stable reference clock CREF, the periodic clocks generated by VCO 10 will be locked onto the reference clock CREF, providing stable operation.
Clock circuit 2 digitally generates an output clock COUT at a selected frequency, in this example, through the operation of multiplexer 14 and D-type flip-flop 16. Multiplexer 14 has a plurality of inputs, each receiving one of the output clock signals C from VCO 10. As noted above, the clock signals C all are at the same frequency but at varying phase relative to one another. The output of multiplexer 14 is applied to the clock input of flip-flop 16, which has its inverting output connected to its D input in toggle form. Accordingly, each rising edge of the selected clock signal C applied by multiplexer 14 clocks the state at the inverting output of flip-flop 16 into its D input, changing the state of flip-flop 16 and thus inverting its output on line COUT. In this manner, the selected phase from VCO 10 operates to effect a half cycle of the output clock signal on line COUT.
Control of the selection of the clock signals by multiplexer 14 is carried out by register 18 and adder 20, in this example. A digital frequency selection is applied on lines FREQ to one input of adder 20, indicating the number of successive phases from VCO 10 that are to elapse between generation of the leading and trailing edges of output clock COUT. The output of adder 20 is applied to register 18 for storage, clocked in by the selected phase from the output of multiplexer 14; the output of register 18 is then applied to the select inputs of multiplexer 14. In this conventional clock circuit 2, where n phases are generated by VCO 10, the number of digital lines FREQ are log.sub.2 n, as are the number of lines communicated from the output of adder 20 to register 18, and from register 18 to multiplexer 14 and to an input of adder 20.
In operation, the current selection value applied to multiplexer 14 by register 18 is added to the phase increment signal on lines FREQ to generate the next edge selection value for use by multiplexer 14. For example, consider the case in which thirty-two phases are issued by VCO 10 in each period of its output clock signals (i.e., n=32). If an edge is to be issued every four phases of the clock signals C from VCO 10, lines FREQ will carry the value 4.sub.10 or 00100.sub.2. In each cycle, adder 20 will add this value of four to the current selection value applied to multiplexer 14, with the sum selecting the next edge that is to be applied to flip-flop 16 to toggle its output In this example, where lines FREQ conveys the value 4.sub.10, the output clock COUT will make a transition every four phases from VCO 10, or eight times within each period of the clock signals C from VCO 10. In effect, therefore, the clock signal COUT will be at four times the frequency of VCO 10, in that a cycle of output clock signal COUT is completed upon every two selected edges from the output of multiplexer 14. The theoretical range of selectable frequencies thus ranges from one-half the frequency of VCO 10 (for FREQ=0, such that the same edge is selected in each cycle), to n/2 times the frequency of VCO 10 (for FREQ=1, so that each phase of clock signals C is issued by multiplexer 14).
According to this known concept, however, the resolution with which the frequency of the synthesized clock signal at line COUT may be selected depends upon the number n of phases of clock signals C generated by VCO 10. For a given VCO frequency, further resolution is obtained only by greatly increasing the complexity of VCO 10 to provide more clock phases at its output. As a result, the applicability of digital clock circuit 2 to extremely precise applications such as video decoders is quite limited.